Modeling and Formal Verification of a Passive Optical Network on Chip Behavior

Luiza Gheorghe Iugan, Gabriela Nicolescu, Ian O'Connor

Abstract


Many of the modern Systems-on-Chip integrate a high density of heterogeneous components such as different processors, a wide range of hardware components, as well as complex interconnects that use different communication protocols. On-chip physical interconnections represent a limiting factor for the performance and energy consumption. Currently, the optical interconnects integrated on chip are a viable alternative for on chip interconnects. However, the access to physical prototyping of these interconnects is a major challenge because this systems require very recent technologies, still difficult to access. Thus, their high-level modeling and validation are mandatory. This paper proposes the modeling and the formal verification for the global validation of the behavior of a passive integrated photonic routing structure using models that are based on timed automata.

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DOI: http://dx.doi.org/10.14279/tuj.eceasst.21.302

DOI (PDF): http://dx.doi.org/10.14279/tuj.eceasst.21.302.289

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